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Ordering number : EN5157C
CMOS LSI
LC72336, 72338
Single-Chip Microcontrollers with Built-In LCD Driver and PLL Circuits
Overview
The LC72336 and LC72338 are single-chip microcontrollers for use in electronic tuners. These products include on chip a PLL circuit that can operate at up to 150 MHz and 1/3 duty LCD drivers. They feature a highly efficient instruction set and powerful hardware.
Package Dimensions
unit: mm 3174-QFP80E
[LC72336, 72338]
Functions
* High-speed programmable divider * Program memory (ROM) -- LC72336: 6143 x 16 bits (12 kB) -- LC72338: 8191 x 16 bits (16 kB) * Data memory (RAM): 512 x 4 bits * All instructions are one-word instructions * Cycle time: 1.33 s * Stack: 8 levels * LCD drivers: Up to 96 segments (1/3 duty, 1/3 bias) * Serial I/O: Up to 3 channels (8-bit 3-wire type) * External interrupts: 2 interrupts (INT0, INT1) Interrupt on rising or falling edge (selectable) * Internal interrupts: 3 interrupt Two built-in timer interrupts and 1 serial I/O interrupt * Nested interrupt levels: 4 levels * D/A converter: 4 channels (8-bit PWM output) * A/D converter: 4 channels (6-bit successive approximation) * General-purpose ports: -- Input ports: 8 -- Output ports: 12 (16 maximum) -- I/O ports: 8 (20 maximum, can be switched between input and output in bit units.) * PLL block: Supports 4 types of dead zone control, and includes a built-in unlock detection circuit. Supports 12 different reference frequencies. * Universal counter: 20 bits (Can be used for either frequency or period measurement.) * Timers: Eight types of time measurement * Beep function: Six beep tones * Reset: Built-in voltage detection type reset circuit * Halt mode: Stops the controller operating clock. * Operating supply voltage: 4.5 to 5.5 V (3.5 to 5.5 V if only the controller block operates.)
SANYO: QIP80E
This LSI can easily use CCB that is SANYO's original bus format.
* CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
O3097HA (OT)/13095HA (OT) No. 5157-1/16
LC72336, 72338 Pin Assignment
Vdd1 Vdd2
No. 5157-2/16
LC72336, 72338 Block Diagram
Vdd1 Vdd2
No. 5157-3/16
LC72336, 72338
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Input voltage Output voltage Symbol VDD max VIN VOUT (1) VOUT (2) IOUT (1) IOUT (2) Output current IOUT (3) IOUT (4) IOUT (5) Allowable power dissipation Operating temperature Storage temperature Note: * Reference value Pd max Topr Tstg All input pins Port PJ All output ports other than VOUT (1) Port PJ PE, PF, PG, PK, PM, PN, EO1, EO2 Ports PB and PC S1 to S32 COM1 to COM3 Ta = -45 to 85C Conditions Ratings -0.3 to +6.5 -0.3 to VDD + 0.3 -0.3 to +15 -0.3 to VDD + 0.3 0 to +5 0 to +3 0 to +1 300 3 300 -40 to +85 -45 to +125 Unit V V V V mA mA mA A mA mW* C C
Allowable Operating Ranges at Ta = -40 to +85C, VDD = 3.5 to 5.5 V
Parameter Symbol VDD (1) Supply voltage VDD (2) VDD (3) VIH (1) Input high-level voltage VIH (2) VIH (3) VIH (4) VIL (1) Input low-level voltage VIL (2) VIL (3) VIL (4) fIN (1) fIN (2) fIN (3) fIN (4) Input frequency fIN (5) fIN (6) fIN (7) fIN (8) VIN (1) Input amplitude VIN (2) VIN (3) Input voltage range VIN (4) Conditions CPU and PLL operating CPU operating Memory retention Ports PE, PH, and PM, HCTR and LCTR (when selected for input) Ports PF, PG, and PK, LCTR (frequency measurement mode), and HOLD SNS Port PA Port PE, PH, and PM, HCTR and LCTR (when selected for input) Port PA, PF, PG, and PK, LCTR (frequency measurement mode) SNS HOLD XIN FMIN: VIN (2), VDD (1) FMIN: VIN (3), VDD (1) AMIN (H): VIN (3), VDD (1) AMIN (L): VIN (3), VDD (1) HCTR: VIN (3), VDD (1) LCTR: VIN (3), VDD (1) LCTR (frequency measurement mode): VIH (2), VIL (2), VDD (1) XIN FMIN FMIN, AMIN, HCTR, LCTR ADI0 to ADI3 min 4.5 3.5 1.3 0.7 VDD 0.8 VDD 2.5 0.6 VDD 0 0 0 0 4.0 10 10 2.0 0.5 0.4 100 1 0.5 0.10 0.07 0 4.5 typ 5.0 max 5.5 5.5 5.5 VDD VDD VDD VDD 0.3 VDD 0.2 VDD +1.3 0.4 VDD 5.0 150 130 40 10 12 500 20 x 103 1.5 1.5 1.5 VDD Unit V V V V V V V V V V V MHz MHz MHz MHz MHz MHz kHz Hz Vrms Vrms Vrms V
No. 5157-4/16
LC72336, 72338 Electrical Characteristics for the Allowable Operating Ranges
Parameter Symbol IIH (1) IIH (2) Input high-level current Conditions XIN: VI = VDD = 5.0 V FMIN, AMIN, HCTR, LCTR: VI = VDD = 5.0 V Ports PA, PE, PF, PG, PH, PK, and PM, SNS, HOLD, HCTR, LCTR: No pull-down resistors on port PA, VI = VDD = 5.0 V, with input mode selected for ports PE, PF, PG, PK, and PM With pull-down resistors on port PA, VI = VDD = 5.0 V XIN: VI = VSS FMIN, AMIN, HCTR, LCTR: VI = VSS Ports PA, PE, PF, PG, PH, PK, and PM, SNS, HOLD, HCTR, LCTR: No pull-down resistors on port PA, VI = VSS, with input mode selected for ports PE, PF, PG, PK, and PM With pull-down resistors on port PA With pull-down resistors on port PA, VDD = 5 V Ports PF, PG, and PK, LCTR (in frequency measurement mode) Ports PB and PC: IO = -1 mA Ports PE, PF, PG, PK, PM, and PN: IO = -1 mA EO1, EO2: IO = -500 A XOUT: IO = -200 A S1 to S32: IO = -20 A COM1, COM2, COM3: IO = -100 A Ports PB and PC: IO = 50 A Ports PE, PF, PG, PK, PM, and PN: IO = 1 mA EO1, EO2: IO = 500 A XOUT: IO = 200 A S1 to S32: IO = 20 A COM1, COM2, COM3: IO = 100 A Port PJ: IO = 5 mA S1 to S32: IO = 20 A S1 to S32: IO = 20 A COM1, COM2, COM3: IO = 100 A COM1, COM2, COM3: IO = 100 A Ports PE, PF, PG, PK, PM, and PN EO1 , EO2 Port PJ ADI0 to ADI3: VDD (1) SNS 2.7 TEST1, TEST2 VDD (1): fIN (2) = 130 MHz, Ta = 25C VDD (2): halt mode*, Ta = 25C (Fig. 1) VDD = 5.5 V, oscillator stopped, Ta = 25C (Fig. 2) VDD = 2.5 V, oscillator stopped, Ta = 25C (Fig. 2) 3.0 10 12 0.45 5 1 0.75 2/3 VDD 1.0 1/3 VDD 1.0 2/3 VDD 1.0 1/3 VDD 1.0 -3.0 -100 -5.0 -1/2 +3.0 +100 +5.0 +1/2 50 3.3 75 0.1 VDD VDD - 2.0 VDD - 1.0 VDD - 1.0 VDD - 1.0 VDD - 1.0 VDD - 1.0 2.0 1.0 1.0 1.0 1.0 1.0 2.0 100 0.2 VDD 2.0 4.0 50 5.0 10 15 30 min 2.0 4.0 typ 5.0 10 max 15 30 Unit A A
IIH (3) IIH (4) IIL (1) IIL (2)
3.0
A
A A A
Input low-level current IIL (3) Input floating voltage Pull-down resistance Hysteresis VIF RPD (1) VH VOH (1) VOH (2) Output high-level voltage VOH (3) VOH (4) VOH (5) VOH (6) VOL (1) VOL (2) VOL (3) Output low-level voltage VOL (4) VOL (5) VOL (6) VOL (7) VMID (1) VMID (2) Output mid-level voltage VMID (3) VMID (4) IOFF (1) Output off leakage current IOFF (2) IOFF (3) AD conversion error Reject pulse width Power-down detection voltage Pull-down resistance -- PREJ VDET RPD (2) IDD (1) Current drain IDD (2) IDD (3) IDD (4)
3.0
A
0.05 VDD 200
V k V V V V V V V V V V V V V V V V V V A nA A LSB s V k mA mA A A
Note: * In case of instruction execution for 20 steps at intervals of 1 ms, with the PLL, counter functions and other functions all stopped.
No. 5157-5/16
LC72336, 72338
Note: 1. Except for the divider resistors used for the bias voltage generation circuit incorporated in the Vdd1 and Vdd2 systems.
Vdd1 To the common and segment drivers Vdd2 The loss due to these resistor is excluded
Test Circuits
Note: With all ports other than those indicated in the figure open. With the segment port function selected for ports PE, PF, PM, and PN. With the output function selected for ports PG and PK.
Note: With all ports other than those indicated in the figure open. With the segment port function selected for ports PE, PF, PM, and PN. With the output function selected for ports PG and PK.
Figure 1 IDD2, IDD3, and IDD4 in Hold Mode
Figure 2 IDD5 in Backup Mode
Pin Functions
Pin No. Symbol I/O I/O type Function These are special-purpose ports for key return signal inputs. Their threshold voltage is set lower than that of other inputs. When a key matrix is formed in conjunction with ports PB and PC, up to three simultaneous key presses can be detected. The pull-down resistors are set up for all four pins by the IOS instruction (Pn = 2, b1). This cannot be specified on an individual pin basis. Input is disabled in clock stop mode. 14 13 12 11 10 9 8 7 PB0 PB1 PB2 PB3 PC0 PC1 PC2 PC3 O Unbalanced CMOS push-pull circuits These are special-purpose ports for key return signal outputs. No diodes for preventing short-circuits due to multiple simultaneous key presses are required since the output transistor circuits are unbalanced CMOS circuits. These pins become high-impedance outputs in clock stop mode. These pins function as high-impedance outputs after a power-on reset and retain that state until an output instruction is executed.
18 17 16 15
PA0 PA1 PA2 PA3 I Inputs with pull-down resistors
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Pin No. Symbol I/O I/O type Function
Shared-function general-purpose output and serial I/O port Inputs are a Schmitt input. The IOS instruction is used to switch between the general-purpose I/O port function and the serial I/O function, as well as between input and output for the general-purpose I/O port function. * When used as a general-purpose I/O port: Input or output can be specified in bit units (bit I/O). These ports are set up to be general-purpose I/O ports with the IOS instruction with Pn = 0. b0 = SI/O0 0 ... General-purpose ports 1 ... SI/O ports The IOS instruction is used to specify input or output in bit units. PG ... Pn = 6 0 ... Input 1 ... Output * When used as a serial I/O port: These ports are set up to be serial I/O ports with the IOS instruction with Pn = 0. The contents of the serial I/O data buffers can be saved and loaded with the INR and OUTR instructions. Note: Pin setup states when used as serial I/O ports: PG0 ... General-purpose I/O PG1 ... SCK0 output in internal clock mode SCK0 input in external clock mode PG2 ... SO0 output PG3 ... SI0 input These ports go to the input disabled high-impedance state in clock stop mode. These ports function as general-purpose input ports after a power-on reset.
6 5 4 3
PG0 PG1/SCK0 PG2/SO0 PG3/SI0 I/O CMOS push-pull
1 80
XIN XOUT
I O
--
4.5 MHz crystal oscillator connections
Charge pump outputs 77 78 EO1 EO2 O CMOS tristate These pins go to the high-impedance state when the HOLD pin is set low in the hold enable state. These pins go to the high-impedance state in clock stop mode, after a power-on reset, and in the PLL stopped state.
76 31, 73
VSS VDD
--
--
Power supply connections
AM VCO (local oscillator) input This pin is selected and the band set using the PLL instruction CW1 (b1 and b0) field. b1 75 AMIN I CMOS amplifier input 1 1 b0 0 1 2 to 40 MHz (SW) 0.5 to 10 MHz (MW, LW) Band
The input signal must be capacitor coupled. Input is disabled if the HOLD pin is set low in the HOLD enabled state. Input is disabled in clock stop mode, after a power-on reset, and in the PLL stopped state.
FM VCO (local oscillator) input This pin is selected using the PLL instruction CW1 field (b1 = 0, b0 = don't care). 74 FMIN I CMOS amplifier input The input signal must be capacitor coupled. Input is disabled if the HOLD pin is set low in the HOLD enabled state. Input is disabled in clock stop mode, after a power-on reset, and in the PLL stopped state.
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LC72336, 72338
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Pin No. Symbol I/O I/O type Function
Shared-function voltage sensing input and general-purpose input port The input threshold voltage is set lower than that of other inputs. * When used as a voltage sensing pin: This pin is used to recognize power failures on recovery from backup (clock stop) mode. An internal sensing flip-flop is used for this determination. The TUL instruction (b2) can be used to test the sense flip-flop. * When used as a general-purpose input port: Use the TUL instruction (b3) to test this pin when it is used as a general-purpose input port. Unlike other input ports, input is not disabled during clock stop mode or a power-on reset. Thus applications must take through currents into consideration if this pin is used as a general-purpose input port.
72
SNS
I
CMOS input
Shared-function universal counter (frequency or period measurement) and generalpurpose input port The IOS instruction (Pn = 3, b3) is used to switch this pin between its universal counter and general-purpose input port functions. * When used for frequency measurement: Select the universal counter function with an IOS instruction (Pn = 3, b3 = 0). Set LCTR frequency measurement mode with a UCS instruction (b3 = 0, b2 = 1). After selecting the measurement time, start the counter with a UCC instruction. The CNTEND flag will be set when the count completes. Since this circuit operates as an AC amplifier in this mode, the input must be capacitor coupled. 71 LCTR I CMOS amplifier input * When used for period measurement: With the universal counter function selected, set period measurement mode with a UCS instruction (b3 = 1, b2 = 0). After selecting the measurement time, start the counter with a UCC instruction. The CNTEND flag will be set when the count completes. Since the bias feedback resistor is switched off in this mode, the input must be DC coupled. * When used as a general-purpose input port: Specify the general-purpose input port function with an IOS instruction (Pn = 3, b3 = 1). Use the INR (b1) internal register (address 0EH) input instruction to read in the input data. Input is disabled in clock stop mode. (The input pin is pulled down.) The universal counter function is selected after a power-on reset. (HCTR frequency measurement mode.)
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LC72336, 72338
Continued from preceding page.
Pin No. Symbol I/O I/O type Function
Shared-function universal counter input and general-purpose input port The IOS instruction (Pn = 3, b3) is used to switch this pin between its universal counter and general-purpose input port functions. * When used for frequency measurement: Select the universal counter function with an IOS instruction (Pn = 3, b2 = 0). Set HCTR frequency measurement mode with a UCS instruction (b3 = 0, b2 = 0). After selecting the measurement time, start the counter with a UCC instruction. The CNTEND flag will be set when the count completes. Since this circuit operates as an AC amplifier in this mode, the input must be capacitor coupled. * When used as a general-purpose input port: Set the general-purpose input port function with an IOS instruction (Pn = 3, b2 = 1). Use the INR (b1) internal register (address 0EH) input instruction to read in the input data. Input is disabled in clock stop mode. (The input pin is pulled down.) The universal counter function is selected after a power-on reset.
70
HCTR
I
CMOS amplifier input
Controls the PLL circuit and clock stop mode. When this pin is set low in the hold enabled state, FMIN and AMIN pin input is disabled and the EO pin goes to the high-impedance state. To switch to clock stop mode, set the HOLDEN flag, set this pin low, and execute a CKSTP instruction. Set this pin high to clear clock stop mode.
69
HOLD
I
CMOS input
Shared-function general-purpose input and A/D converter input port The IOS instruction (Pn = 7) is used to switch these pins between the general-purpose and A/D converter input port functions. * When used as a general-purpose input port: Set the general-purpose input port function (in bit units) with the IOS instruction (Pn = 7). 68 67 66 65 PH0/ADI0 PH1/ADI1 PH2/ADI2 PH3/ADI3 I CMOS input Analog input * When used for A/D converter input: Set the A/D converter input port function with an IOS instruction (Pn = 7). Specify the pin to convert with an IOS instruction (Pn = 1). Start the conversion with a UCC instruction (b2). The ADCE flag is set when the conversion has completed. Note: Since input is disabled, low will always be returned if an input instruction (the IN instruction) is executed for a port specified for A/D converter input. (In other words, the port must be set to the general-purpose input function before the input instruction is executed.) Input is disabled in clock stop mode. The general-purpose input function is selected after a power-on reset.
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Pin No. Symbol I/O I/O type Function Shared-function general-purpose and D/A converter output port The IOS instruction (Pn = 9) is used to switch these pins between the general-purpose and D/A converter output port functions. Since these pins are open drain circuits, pull-up resistors are required in external circuits accepting these outputs. 64 63 62 61 PJ0/DAC0 PJ1/DAC1 PJ2/DAC2 PJ3/DAC3 O N-channel open drain * When used as a general-purpose port: Set the general-purpose input port function with the IOS instruction (Pn = 9). * When used for D/A converter output: Use the IOS instruction (Pn = 9) to switch the port in bit units. D/A converter data is loaded into the DAC0 to DAC3 specified with the DAC instruction. Although a PWM waveform is output as soon as the port is switched, after data is loaded, the data prior to that load is output for up to 114 s (1/8.79 kHz). In clock stop mode, these outputs go to the transistor off (high output) state. The general-purpose output port function is selected after a power-on reset, and the outputs go to the transistor off (high output) state.
Shared-function general-purpose I/O and external interrupt port There is no instruction that switches between the general-purpose port and the external interrupt pin functions. Rather, the corresponding pin becomes an input-only pin (output disabled) at the point where the external interrupt enable flag for that pin is set. * When used as a general-purpose I/O port: Input or output can be specified in bit units (bit I/O). The IOS instruction is used to specify input or output in bit units. I/O CMOS push-pull * When used as external interrupt pins: These pins are enabled by setting the external interrupt enable flags (INT0EN and INT1EN) in status register 2. At that point the pin is automatically set up to be an input port. The status register 1 interrupt enable flag (INTEN) must also be set to enable interrupt operation. Use the IOS instruction (Pn = 3, b1 = INT1, b0 = INT0) to select rising or falling edge detection. Input is disabled with the pins in the high-impedance state in clock stop mode. The general-purpose input port function is selected after a power-on reset.
22 21 20 19
PK0/INT0 PK1/INT1 PK2 PK3
60 59 79 2 58 57 56
Vdd1 Vdd2 TEST1 TEST2 COM1 COM2 COM3 O
-- -- --
Apply the LCD drive bias 2/3 voltage to this pin. Apply the LCD drive bias 1/3 voltage to this pin. LSI test pin This pin must be left open or connected to ground. LCD driver common output pins
CMOS 3-value output
This drive circuit implements a 1/3-duty, 1/3-bias drive scheme. These pins are fixed at the low level in clock stop mode. These pins are fixed at the low level after a power-on reset. LCD driver segment output pins This drive circuit implements a 1/3-duty, 1/3-bias drive scheme.
55 to 40
S1 to S16
O
CMOS 3-value output
The frame frequency is 100 Hz. These pins are fixed at the low level in clock stop mode. These pins are fixed at the low level after a power-on reset.
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Continued from preceding page.
Pin No. Symbol I/O I/O type Function
Shared-function LCD driver segment output, general-purpose I/O, and serial I/O port The IOS instruction is used to switch between the LCD driver segment output, generalpurpose I/O, and serial I/O functions, and to switch between input and output for the general-purpose input port function. * When used for segment output: The function can be specified in bit units. Segment output is specified with the IOS instruction (Pn = 0DH). b0 = S17/PE0 0 ... Segment output b1 = S18/PE1 1 ... PE0 to PE3 output b2 = S19/PE2 b3 = S20/PE3 * When used as a general-purpose I/O port: Input or output can be specified in bit units (1-bit I/O). The general-purpose I/O port function is specified with the IOS instruction (Pn = 0). b2 = SI/O2 0 ... General-purpose port 1 ... SI/O port Input or output is specified with the IOS instruction in bit units. PE ... Pn = 4 0 ... Input 1 ... Output * When used as a serial I/O port: The serial I/O port function is specified with the IOS instruction (Pn = 0). The contents of the serial I/O data buffer can be saved and loaded with the INR and OUTR instructions. Note: Pin setup states when used as a serial I/O port: PE0 ... General-purpose I/O PE1 ... SCK2 output in internal clock mode SCK2 input in external clock mode PE2 ... SO2 output PE3 ... SI2 input In clock stop mode, if this port is used as a general-purpose I/O port or as a serial I/O port, the pins go to the input disabled high-impedance state. If used for segment output, the pins are fixed at the low level. The segment output port function is selected after a power-on reset.
39 38 37 36
S17/PE0 S18/PE1/SCK2 S19/PE2/SO2 S20/PE3/SI2 I/O
CMOS 3-value output and push-pull
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Pin No. Symbol I/O I/O type Function
Shared-function LCD driver segment output, general-purpose I/O, and serial I/O port The PF0 to PF3 inputs are Schmitt inputs. The IOS instruction is used to switch between the LCD driver segment output, generalpurpose I/O, and serial I/O functions, and to switch between input and output for the general-purpose input port function. * When used for segment output: The function is specified in 4-bit units. Segment output is specified with the IOS instruction (Pn = 0EH). b0 = S21 to S24/PF0 to PF3 0 ... Segment output 1 ... PF0 to PF3 output * When used as a general-purpose I/O port: Input or output can be specified in bit units (1-bit I/O). The general-purpose I/O port function is specified with the IOS instruction (Pn = 0). b1 = SI/O1 0 ... General-purpose port 1 ... SI/O port Input or output is specified with the IOS instruction in bit units. PF ... Pn = 5 0 ... Input 1 ... Output * When used as a serial I/O port: The serial I/O port function is specified with the IOS instruction (Pn = 0). The contents of the serial I/O data buffer can be saved and loaded with the INR and OUTR instructions. Note: Pin setup states when used as a serial I/O port: PF0 ... General-purpose I/O PF1 ... SCK1 output in internal clock mode SCK1 input in external clock mode PF2 ... SO1 output PF3 ... SI1 input In clock stop mode, if this port is used as a general-purpose I/O port or as a serial I/O port, the pins go to the input disabled high-impedance state. If used for segment output, the pins are fixed at the low level. The segment output port function is selected after a power-on reset.
35 34 33 32
S21/PF0 S22/PF1/SCK1 S23/PF2/SO1 S24/PF3/SI1 I/O CMOS 3-value output and push-pull
Shared-function LCD driver segment output and general-purpose I/O port The IOS instruction is used to switch between the LCD driver segment output and the general-purpose I/O functions, and to switch between input and output for the generalpurpose input port function. * When used for segment output: The function is specified in 4-bit units. Segment output is specified with the IOS instruction (Pn = 0EH). b1 = S25 to S28/PM0 to PM3 0 ... Segment output 1 ... PF0 to PF3 output * When used as a general-purpose I/O port: Input or output can be specified in bit units (1-bit I/O). Input or output is specified with the IOS instruction in bit units. PM ... Pn = 0CH 0 ... Input 1 ... Output In clock stop mode, if this port is used as a general-purpose I/O port, the pins go to the input disabled high-impedance state. If used for segment output, the pins are fixed at the low level. The segment output port function is selected after a power-on reset.
30 29 28 27
S25/PM0 S26/PM1 S27/PM2 S28/PM3 I/O CMOS 3-value output and push-pull
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Pin No. Symbol I/O I/O type Function
Shared-function segment output, general-purpose output, and beep tone output port The IOS instruction is used to switch between the segment output port and the PN0 to PN3 functions. The BEEP instruction is used to switch between the general-purpose output port and the beep tone output functions. * When used for segment output: The function can be specified in 3-bit units. Segment output is specified with the IOS instruction (Pn = 0EH). b2 = S29 to S32/PN0 to PN3 0 ... Segment output 1 ... PN0 to PN3 output O CMOS 3-value output and push-pull * When used as a general-purpose output port: The general-purpose output port function is selected with the BEEP instruction (b3 = 0). PN1 to PN3 are dedicated general-purpose output function pins. * When used as the BEEP output pin: Beep tone output is specified with the BEEP instruction (b3 = 1). The frequency is specified with the BEEP instruction (b0, b1, and b2). When the beep tone function is specified, executing an output instruction will only overwrite the contents of the internal latch. It will have no effect on the output whatsoever. In clock stop mode, if this port is used as a general-purpose output port, the pins go to the input disabled high-impedance state. If used for segment output, the pins are fixed at the low level. The segment output port function is selected after a power-on reset.
26 25 24 23
S29/PN0/BEEP S30/PN1 S31/PN2 S32/PN3
No. 5157-13/16
LC72336, 72338 LC723336 and LC72338 Instruction Table Abbreviations: ADDR: Program memory address b: Borrow C: Carry DH: Data memory address high (row address) [2 bits] DL: Data memory address low (column address) [4 bits] I: Immediate data [4 bits] M: Data memory address N: Bit position [4 bits] Pn: Port number [4 bits] r: General register (one of the locations 00 to 0FH in bank) Rn: Register number [4 bits] ( ): Contents of register or memory ( )N: Contents of bit N of register or memory
Instruction group Operand Mnemonic 1st AD ADS Addition instructions AC ACS AI AIS AIC AICS SU SUS SB r r r r M M M M r r r 2nd M M M M I I I I M M M Add M to r Add M to r, then skip if carry Add M to r with carry Add M to r with carry, then skip if carry Add I to M Add I to M, then skip if carry Add I to M with carry Add I to M with carry, then skip if carry Subtract M from r Subtract M from r, then skip if borrow Subtract M from r with borrow Subtract M from r with borrow, then skip if borrow Subtract I from M Subtract I from M, then skip if borrow Subtract I from M with borrow Subtract I from M with borrow, then skip if borrow Skip if r equal to M Skip if M equal to I Skip if r not equal to M Skip if r is greater than or equal to M Skip if M is greater than or equal to I Skip if M is less than I r (r) + (M) r (r) + (M) skip if carry r (r) + (M) + C r (r) + (M) + C skip if carry M (M) + I M (M) + I skip if carry M (M) + I + C M (M) + I + C skip if carry r (r) - (M) r (r) - (M) skip if borrow r (r) - (M) - b r (r) - (M) - b skip if borrow M (M) - I M (M) - I skip if borrow M (M) - I - b M (M) - I - b skip if borrow (r) - (M) skip if zero (M) - I skip if zero (M) - I skip if not zero (r) - (M) skip if not borrow (M) - I skip if not borrow (M) - I skip if borrow Function Operation D15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH 7654 DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL 3 2 1 D0 r r r r I I I I r r r Machine code
Subtraction instructions
SBS SI SIS SIB
r M M M
M I I I
0 0 0 0
1 1 1 1
1 1 1 1
0 1 1 1
1 0 0 1
1 0 1 0
r I I I
SIBS
M
I
0
1
1
1
1
1
I
SEQ Comparison instructions SEQI SNEI SGE SGEI SLEI
r M M r M M
M I I M I I
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
1 1 0 1 1 0
0 0 0 1 1 1
0 1 1 0 1 1
DH DH DH DH DH DH
DL DL DL DL DL DL
r I I r I I
Continued on next page. No. 5157-14/16
LC72336, 72338
Continued from preceding page.
Instruction group Operand Mnemonic 1st AND Logical operation instructions ANDI OR ORI EXL EXLI LD ST Transfer instructions MVRD r M r M r M r M r 2nd M I M I M I M r M AND M with r AND I with M OR M with r OR I with M Exclusive OR M with r Exclusive OR I with M Load M to r Store r to M Move M to destination M referring to r in the same row Move source M referring to r to M in the same row Move M to M in the same row Move I to M Test M bits, then skip if all bits specified are true Test M bits, then skip if all bits specified are false Jump to the address Call subroutine Return from subroutine Return from subroutine and skip Return from subroutine with bank data Return from subroutine with bank data and skip Return from interrupt r (r) AND (M) M (M) AND I r (r) OR (M) M (M) OR I r (r) XOR (M) M (M) XOR I r (M) M (r) [DH, Rn] (M) Function Operation D15 14 13 12 11 10 9 8 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 DH DH DH DH DH DH DH DH DH 7654 DL DL DL DL DL DL DL DL DL 3 2 1 D0 r I r I r I r r r Machine code
MVRS
M
r
M [DH, Rn] [DH, DL1] [DH, DL2] MI if M (N) = all "1", then skip if M (N) = all "0", then skip PC ADDR Stack (PC) + 1 PC Stack PC Stack + 1 PC Stack BANK Stack PC Stack + 1 BANK Stack PC Stack BANK Stack CARRY Stack (Status reg I) N1 (Status reg I) N0 if (Status reg I) N = all "1", then skip if (Status reg I) N = all "0", then skip
1
1
0
1
1
1
DH
DL
r
MVSR MVI Bit test instructions TMT
M1 M M
M2 I N
1 1 1
1 1 1
1 1 1
0 0 1
0 0 0
0 1 0
DH DH DH
DL1 DL DL
DL2 I N
TMF JMP CAL RT RTS RTB RTBS
M
N
1 1 1 0 0 1 1
1 0 0 0 0 1 1
1 0 1 0 0 1 1
1
0
1
DH
DL
N
Jump and subroutine call instructions
ADDR ADDR
ADDR (13 bits) ADDR (13 bits) 0 0 1 1 0 0 1 1 0 0 1 1 00 00 11 11 1000 1010 1100 1101
RTI
0
0
0
0
0
0
00
1001
SS Status register instructions RS TST TSF F/F test instruction
I I I I
N N N N
Set status register Reset status register Test status register true Test status register false
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
11 11 11 11
000 001 01 10 I I
I I
N N N N
TUL
N
Test unlock F/F then skip if it has not been set
if Unlock F/F (N) = all "0", then skip
0
0
0
0
0
0
00
1101
N
Internal register transfer instructions
PLL DAC INR OUTR
M I M M
r
Load M to PLL registers
PLL reg PLL data DAC reg DAC data
1 0 0 0
1 0 0 0
1 0 1 1
1 0 1 1
1 0 1 1
0 0 0 1
DH 00 DH DH
DL 0011 DL DL
r I Rn Rn
Rn Rn
Input register/port data to M Output contents of M to register/port
M (Rn reg) Rn reg (M)
Continued on next page. No. 5157-15/16
LC72336, 72338
Continued from preceding page.
Instruction group Operand Mnemonic 1st SIO Hardware control instructions UCS UCC BEEP DZC IOS TMS Bank switching instruction I1 I I I I Pn I I 2nd I2 Serial I/O control Set I to UCCW1 Set I to UCCW2 Beep control Dead zone control Set port control word SIO I1, I2 UCCW1 I UCCW2 I BEEP reg I DZC reg I IOS reg Pn I Timmer reg I Function Operation D15 14 13 12 11 10 9 8 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 01 00 00 00 00 10 00 7654 I1 0001 0010 0110 1011 Pn 1100 3 2 1 D0 I2 I I I I I I Machine code
BANK
I
Select bank
BANK I
0
0
0
0
0
0
00
0111
I
LCDA LCD control instructions LCDB LCPA LCPB IN OUT I/O instructions SPB RPB TPT
M M M M M M Pn Pn Pn
I I I I Pn Pn N N N
Output segment pattern to LCD digit direct Output segment pattern to LCD digit through Logic Array Input port data to M Output contents of M to port Set port bits Reset port bits Test port bits, then skip if all bits specified are true Test port bits, then skip if all bits specified are false Halt mode control Clock stop
LCD (DIGIT) M LCD (DIGIT) Logic Array M M (Pn) Pn M (Pn) N 1 (Pn) N 0 if (Pn) N = all "1", then skip if (Pn) N = all "0", then skip HALT reg I, then CPU clock stop Stop X'tal OSC if HOLD = 0 Shift r right with carry
1 1 1 1 1 1 0 0 1
1 1 1 1 1 1 0 0 1
0 0 0 0 1 1 0 0 1
0 0 0 0 0 0 0 0 1
0 0 1 1 1 1 0 0 1
0 1 0 1 0 1 0 0 1
DH DH DH DH DH DH 10 11 00
DL DL DL DL DL DL Pn Pn Pn
DIGIT DIGIT DIGIT DIGIT Pn Pn N N N
TPF Other instructions
Pn
N
1
1
1
1
1
1
01
Pn
N
HALT CKSTP SHR NOP
I
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
00 00 00 00
0100 0101 1110 0000
I
r No operation
r
No operation
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: y Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 1997. Specifications and information herein are subject to change without notice. PS No. 5157-16/16

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